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pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 integrated circuits objective data sheet supersedes data of 2004 jul 28
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2 2004 sep 29 features ? 1-of-2 bi-directional translating switches ? i 2 c interface logic; compatible with smbus standards ? 2 active-low interrupt inputs ? active-low interrupt output ? active-low reset input ? 2 address pins allowing up to 4 devices on the i 2 c-bus ? channel selection via i 2 c-bus, in any combination ? power up with all switch channels deselected ? low rds on switches ? allows voltage level translation between 1.8 v, 2.5 v, 3.3 v and 5 v buses ? no glitch on power-up ? supports hot insertion ? low stand-by current ? operating power supply voltage range of 2.3 v to 5.5 v ? 5 v tolerant inputs ? 0 khz to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v per jesd22-c101 ? latchup testing is done to jesdec standard jesd78 which exceeds 100 ma ? packages offered: so14, tssop14 description the pca9543a is a bi-directional translating switch, controlled by the i 2 c-bus. the scl/sda upstream pair fans out to two downstream pairs, or channels. any individual scx/sdx channels or combination of channels can be selected, determined by the contents of the programmable control register. two interrupt inputs, int0 to int3 , one for each of the downstream pairs, are provided. one interrupt output int , which acts as an and of the two interrupt inputs, is provided. an active-low reset input allows the pca9543a to recover from a situation where one of the downstream i 2 c-buses is stuck in a low state. pulling the reset pin low resets the i 2 c state machine and causes all the channels to be deselected, as does the internal power on reset function. the pass gates of the switches are constructed such that the v dd pin can be used to limit the maximum high voltage which will be passed by the pca9543a. this allows the use of different bus voltages on each scx/sdx pair, so that 1.8 v, 2.5 v, or 3.3 v parts can communicate with 5 v parts without any additional protection. external pull-up resistors pull the bus up to the desired voltage level for each channel. all i/o pins are 5 v tolerant. pin configuration 1 2 3 4 5 6 78 9 10 11 12 13 14 a0 a1 reset int0 sd0 sc0 v ss v dd sda scl sd1 sc1 int1 int sw00803 figure 1. pin configuration pin description pin number symbol function 1 a0 address input 0 2 a1 address input 1 3 reset active low reset input 4 int0 interrupt input 0 5 sd0 serial data 0 6 sc0 serial clock 0 7 v ss supply ground 8 int1 interrupt input 1 9 sd1 serial data 1 10 sc1 serial clock 1 11 int interrupt output 12 scl serial clock line 13 sda serial data line 14 v dd supply voltage ordering information packages temperature range order code topside mark drawing number 14-pin plastic so 40 c to +85 c PCA9543AD PCA9543AD sot108-1 14-pin plastic tssop 40 c to +85 c pca9543apw pa9543a sot402-1 standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 3 block diagram sw02265 sc0 sc1 sd0 sd1 v ss scl v dd sda input filter power-on reset i 2 c-bus control a0 int[01] int logic int a1 reset pca9543a switch control logic figure 2. block diagram
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 4 device address following a start condition the bus master must output the address of the slave it is accessing. the address of the pca9543a is shown in figure 3. to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low. a1 a0 00 sw00893 1 1 1 r/w fixed hardware selectable figure 3. slave address the last bit of the slave address defines the operation to be performed. when set to logic 1, a read is selected while a logic 0 selects a write operation. control register following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9543a, which will be stored in the control register. if multiple bytes are received by the pca9543a, it will save the last byte received. this register can be written and read via the i 2 c-bus. sw01025 channel selection bits interrupt bits (read only) (read/write) 6 7 channel 0 channel 1 int0 int1 int1 int0 x x b1 b0 6 5 4 2 1 0 7 3 figure 4. control register control register definition one or several scx/sdx downstream pair, or channel, is selected by the contents of the control register. this register is written after the pca9543a has been addressed. the 2 lsbs of the control byte are used to determine which channel is to be selected. when a channel is selected, the channel will become active after a stop condition has been placed on the i 2 c-bus. this ensures that all scx/sdx lines will be in a high state when the channel is made active, so that no false conditions are generated at the time of connection. table 1. control register; write e channel selection/ read e channel status d7 d6 int1 int0 d3 d2 b1 b0 command x x x x x x x 0 channel 0 disabled x x x x x x x 1 channel 0 enabled x x x x x x 0 x channel 1 disabled x x x x x x 1 x channel 1 enabled 0 0 0 0 0 0 0 0 no channel selected; power-up/reset default state note: channel 0 and 1 can be enabled at the same time. care should be taken not to exceed the maximum bus capacitance. interrupt handling the pca9543a provides 2 interrupt inputs, one for each channel, and one open drain interrupt output. when an interrupt is generated by any device, it will be detected by the pca9543a and the interrupt output will be driven low. the channel need not be active for detection of the interrupt. a bit is also set in the control register. bits 4 5 of the control register correspond to the int0 and int1 inputs of the pca9543a, respectively. therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. the master can then address the pca9543a and read the contents of the control register to determine which channel contains the device generating the interrupt. the master can then reconfigure the pca9543a to select this channel, and locate the device generating the interrupt and clear it. it should be noted that more than one device can be providing an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. the interrupt inputs may be used as general purpose inputs if the interrupt feature is not required. if unused, interrupt input(s) must be connected to v dd through a pull-up resistor. table 2. control register read e interrupt 7 6 int1 int0 3 2 b1 b0 command x x x 0 x x x x no interrupt on channel 0 x x x 1 x x x x interrupt on channel 0 x x 0 x x x x x no interrupt on channel 1 x x 1 x x x x x interrupt on channel 1 note: the two interrupts can be active at the same time. reset input the reset input is an active-low signal which may be used to recover from a bus fault condition. by asserting this signal low for a minimum of t wl , the pca9543a will reset its registers and i 2 c state machine and will deselect all channels. the reset input must be connected to v dd through a pull-up resistor. power-on reset when power is applied to v dd , an internal power-on reset holds the pca9543a in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pca9543a registers and i 2 c state machine are initialized to their default states, all zeroes causing all the channels to be deselected. thereafter, v dd must be lowered below 0.2 v to reset the device.
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 5 voltage translation the pass gate transistors of the pca9543a are constructed such that the v dd voltage can be used to limit the maximum voltage that will be passed from one i 2 c-bus to another. 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 v pass vs. v dd 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v pass v dd minimum typical maximum sw00820 2.0 figure 5. v pass voltage figure 5 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in the dc characteristics section of this datasheet). in order for the pca9543a to act as a voltage translator, the v pass voltage should be equal to, or lower than the lowest bus voltage. for example, if the main bus was running at 5 v, and the downstream buses were 3.3 v and 2.7 v, then v pass should be equal to or below 2.7 v to effectively clamp the downstream bus voltages. looking at figure 5, we see that v pass (max.) will be at 2.7 v when the pca9543a supply voltage is 3.5 v or lower so the pca9543a supply voltage could be set to 3.3 v. pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see figure 12). more information can be found in application note an262 pca954x family of i 2 c/smbus multiplexers and switches.
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 6 characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 6). sda scl sw00363 data line stable; data valid change of data allowed figure 6. bit transfer start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 7). system configuration a device generating a message is a transmitter: a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 8). sda scl sw00365 s p sda scl start condition stop condition figure 7. definition of start and stop conditions master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl sw00366 i 2 c multiplexer slave figure 8. system configuration
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 7 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. eac h byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter whereas the master ge nerates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges h as to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge r elated clock pulse, set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. data output by transmitter scl from master sw00368 data output by receiver 12 89 s start condition clock pulse for acknowledgement acknowledge not acknowledge figure 9. acknowledgement on the i 2 c-bus sda s0a a 11 1 0 0a1a0 slave address start condition r/w acknowledge from slave acknowledge from slave b0 control register xp sw00807 b1 xx xx x figure 10. write control register sda s1a na 1 1 1 0 0 a1 a0 start condition r/w acknowledge from slave control register p stop condition last byte sw00808 slave address no acknowledge from master b0 int0 b1 int1 x xx x figure 11. read control register
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 8 typical application pca9543a v = 2.7 5.5 v sd0 sc0 v = 2.7 5.5 v sd1 sc1 a1 a0 v ss sda scl reset v dd = 3.3 v v dd = 2.7 5.5 v i 2 c smbus master sw02266 sda scl int int1 int0 channel 0 channel 1 note: 1. if the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required. if the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pull-up resistor is not required. the interrupt inputs should not be left floating. see note (1) see note (1) figure 12. typical application absolute maximum ratings 1, 2 in accordance with the absolute maximum rating system (iec 134).voltages are referenced to gnd (ground = 0 v). symbol parameter conditions rating unit v dd dc supply voltage 0.5 to +7.0 v v i dc input voltage 0.5 to +7.0 v i i dc input current 20 ma i o dc output current 25 ma i dd supply current 100 ma i ss supply current 100 ma p tot total power dissipation 400 mw t stg storage temperature range 60 to +150 c t amb operating ambient temperature 40 to +85 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c.
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 9 dc characteristics v dd = 2.3 v to 3.6 v; v ss = 0 v; t amb = 40 c to +85 c; unless otherwise specified. (see page 10 for v dd = 3.6 v to 5.5 v) symbol parameter test conditions limits unit symbol parameter test conditions min typ max unit supply v dd supply voltage 2.3 e 3.6 v i dd supply current operating mode; v dd = 3.6 v; no load; v i = v dd or v ss ; f scl = 100 khz e 40 100 m a i stb standby current standby mode; v dd = 3.6 v; no load; v i = v dd or v ss ; f scl = 0 khz e 0.2 1 m a v por power-on reset voltage (note 1) no load; v i = v dd or v ss e 1.6 2.1 v input scl; input/output sda v il low-level input voltage 0.5 e 0.3v dd v v ih high-level input voltage 0.7v dd e 6 v i o low level out p ut current v ol = 0.4 v 3 e ma i ol low - le v el o u tp u t c u rrent v ol = 0.6 v 6 e ma i l leakage current v i = v dd or v ss 1 e +1 m a c i input capacitance v i = v ss e 9 10 pf select inputs a0 to a1 / int0 to int1 / reset v il low-level input voltage 0.5 e +0.3v dd v v ih high-level input voltage 0.7v dd e v dd + 0.5 v i li input leakage current v i = v dd or v ss 1 e +1 m a c i input capacitance v i = v ss e 1.6 3 pf pass gate r o switch resistance v cc = 3.0 v to 3.6 v; v o = 0.4 v; i o = 15 ma 5 11 30 w r on s w itch resistance v cc = 2.3 v to 2.7 v; v o = 0.4 v; i o = 10 ma 7 16 55 w v swin = v dd = 3.3 v; i swout = 100 m a e 1.9 e v switch out p ut voltage v swin = v dd = 3.0 v to 3.6 v; i swout = 100 m a 1.6 e 2.8 v v pass s w itch o u tp u t v oltage v swin = v dd = 2.5 v; i swout = 100 m a e 1.5 e v v swin = v dd = 2.5 v to 2.7 v; i swout = 100 m a 1.1 e 2.0 i l leakage current v i = v dd or v ss 1 e +1 m a c io input/output capacitance v i = v ss e 3 5 pf int output i ol low-level output current v ol = 0.4 v 3 e e ma i oh high-level output current e e +100 m a note: 1. v dd must be lowered to 0.2 v in order to reset part.
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 10 dc characteristics v dd = 3.6 v to 5.5 v; v ss = 0 v; t amb = 40 c to +85 c; unless otherwise specified. (see page 9 for v dd = 2.3 v to 3.6 v) symbol parameter test conditions limits unit symbol parameter test conditions min typ max unit supply v dd supply voltage 3.6 e 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; v i = v dd or v ss ; f scl = 100 khz e 65 100 m a i stb standby current standby mode; v dd = 5.5 v; no load; v i = v dd or v ss ; f scl = 0 khz e 0.2 1 m a v por power-on reset voltage no load; v i = v dd or v ss e 1.7 2.1 v input scl; input/output sda v il low-level input voltage 0.5 e 0.3v dd v v ih high-level input voltage 0.3v dd e 6 v i o low level out p ut current v ol = 0.4 v 3 e e ma i ol low - le v el o u tp u t c u rrent v ol = 0.6 v 6 e e ma i il low-level input current v i = v ss 1 e 1 m a i ih high-level input current v i = v dd 1 e 1 m a c i input capacitance v i = v ss e 9 10 pf select inputs a0 to a1 / int0 to int1 / reset v il low-level input voltage 0.5 e +0.3v dd v v ih high-level input voltage 0.7v dd e v dd + 0.5 v i li input leakage current v i = v dd or v ss 1 e +50 m a c i input capacitance v i = v ss e 2 5 pf pass gate r on switch resistance v cc = 4.5 v to 5.5 v; v o = 0.4 v; i o = 15 ma 4 9 24 w v switch out p ut voltage v swin = v dd = 5.0 v; i swout = 100 m a e 3.6 e v v pass s w itch o u tp u t v oltage v swin = v dd = 4.5 v to 5.5 v; i swout = 100 m a 2.6 e 4.5 v i l leakage current v i = v dd or v ss 1 e +100 m a c io input/output capacitance v i = v ss e 3 5 pf int output i ol low-level output current v ol = 0.4 v 3 e e ma i oh high-level output current e e +100 m a note: 1. v dd must be lowered to 0.2 v in order to reset part.
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 11 ac characteristics symbol parameter standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t pd propagation delay from sda to sd n or scl to sc n e 0.3 1 e 0.3 1 ns f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 e 1.3 e m s t hd;sta hold time (repeated) start condition after this period, the first clock pulse is generated 4.0 e 0.6 e m s t low low period of the scl clock 4.7 e 1.3 e m s t high high period of the scl clock 4.0 e 0.6 e m s t su;sta set-up time for a repeated start condition 4.7 e 0.6 e m s t su;sto set-up time for stop condition 4.0 e 0.6 e m s t hd;dat data hold time 0 2 3.45 0 2 0.9 m s t su;dat data set-up time 250 e 100 e ns t r rise time of both sda and scl signals e 1000 20 + 0.1c b 3 300 ns t f fall time of both sda and scl signals e 300 20 + 0.1c b 3 300 m s c b capacitive load for each bus line e 400 e 400 m s t sp pulse width of spikes which must be suppressed by the input filter e 50 e 50 ns t vd:datl data valid (hl) 4 e 1 e 1 m s t vd:dath data valid (lh) 4 e 0.6 e 0.6 m s t vd:ack data valid acknowledge e 1 e 1 m s int t iv intn to int active valid time e 4 e 4 m s t ir intn to int inactive delay time e 2 e 2 m s l pwr low level pulse width rejection or intn inputs 1 e 1 e ns h pwr high level pulse width rejection or intn inputs 500 e 500 e ns reset t wl(rst) pulse width low reset 4 e 4 e ns t rst reset time (sda clear) 500 e 500 e ns t rec:sta recovery to start 0 e 0 e ns notes: 1. pass gate propagation delay is calculated from the 20 w typical r on and and the 15 pf load capacitance. 2. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the vih min of the scl signal) in order to bridge the undefined region of the falling edge of scl. 3. c b = total capacitance of one bus line in pf. 4. measurements taken with 1 k w pull-up resistor and 50 pf load. t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl su00645 figure 13. definition of timing on the i 2 c-bus
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 12 so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 13 tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 14 revision history rev date description _2 20040929 objective data sheet (9397 750 13988). supersedes data of 2004 jul 28 (9397 750 13299). modifications: ? table 1 acontrol register; writeechannel selection / readechannel statuso on page 4: add `no channel selected; power-up/reset default state' row to bottom of table. ? ac characterists table on page 11: add note 4 and references to it at parameters t vd;datl and t vd;dath . _1 20040728 objective data sheet (9397 750 13299).
philips semiconductors objective data sheet pca9543a 2-channel i 2 c switch with interrupt logic and reset 2004 sep 29 15 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 09-04 document order number: 9397 750 13988

data sheet status [1] objective data sheet preliminary data sheet product data sheet product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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